1. Field of the Invention
The present invention relates to a semiconductor memory and a method of manufacturing the same, and more specifically, it relates to a semiconductor memory such as a dynamic RAM (random access memory) which stores data by presence/absence of stored charges and a method of manufacturing the same.
2. Description f the Prior Art
A well-known example of a conventional semiconductor memory is a dynamic RAM, which stores data by presence/absence of stored charges. A method of manufacturing such a dynamic RAM is disclosed in, e.g., "Building a Dynamic RAM with SMOS", Electronic Design, Mar. 18, 1982, p. 233.
FIG. 1 is a sectional view showing an example of such a conventional semiconductor memory, which is disclosed in Japanese Patent Laying-Open Gazette No. 210665/1982, for example.
Description is now made on the structure of the conventional semiconductor memory as shown in FIG. 1. Referring to FIG. 1, p.sup.+ -type impurity is selectively implanted and diffused in a p.sup.- -type semiconductor substrate 1 to form a p.sup.+ -type region 2 elements and preventing inversion and parasitism, while an insulator film 3 for isolating elements is simultaneously formed on the same. Further, p.sup.+ -type impurity is implanted and diffused by using the insulator film 3 as a mask, to form a p.sup.+ -type region 4 in the p.sup.- -type semiconductor substrate 1 being higher in impurity concentration than the p.sup.- -type substrate 1 as an operating region. Thereafter an n.sup.+ -type region 5 serving as a charge storage region for storing data and an n.sup.+ -type region 6 serving as a bit line are formed to be enclosed by the p.sup.+ -type region 4. A gate oxide film 7 is formed on these regions, and a first layer gate electrode 8 and a second layer gate electrode 9 are formed on the same. These gate electrodes 8 and 9 are isolated from each other by an interlayer insulation film 10. The first layer gate electrode 8 is connected to a power supply (not shown) through a terminal 11, while the second layer gate electrode 9 is connected to a word line (not shown) through a terminal 12. A depletion layer 13 is defined around the n.sup.+ -type region 5 and another depletion layer 14 is defined around the n.sup.+ -type region 6. For convenience of illustration, interconnection parts and a protective film are omitted in FIG. 1. Further, while the n.sup.+ type region 5 is illustrated as an n.sup.+ -type diffusion region in FIG. 1 for convenience of illustration, generally a positive potential is applied to the first layer gate electrode 8 to induce an n.sup.+ -type inversion layer on a surface portion of the p.sup.+ -type region corresponding to the n.sup.+ -type region 5 through the gate insulator film 7, thereby to store charges therein.
In the conventional semiconductor memory as shown in FIG. 1, a bus transistor is formed in the p.sup.+ -type region 4 which is higher in impurity concentration than the semiconductor substrate 1, and the threshold voltage of this bus transistor is generally set to be higher than that of a peripheral transistor in consideration of stable operation of the memory. When the threshold voltage defined by the impurity concentration of the p.sup.+ -type region 4 is too high, the threshold voltage of the bus transistor can be controlled by n.sup.+ -type channel dose after formation of n.sup.+ -type regions 5 and 6. Description is now made on the operation of the semiconductor memory as shown in FIG. 1.
In the semiconductor memory as shown in FIG. 1, a state in which the n.sup.+ -type region 5 serving as a charge storage region of the memory cell stores electrons is defined as "0" and a state in which the same stores no charge is defined as "1". The potential of the n.sup.+ -type region 6 serving as a bit line is precharged at a prescribed level by a sense amplifier (not shown). When the potential of a word line is increased and that of the second layer gate electrode 9, which is connected to the word line for serving as a transfer gate, exceeds the threshold voltage, a channel of an n.sup.+ -type inversion layer is formed directly under the gate electrode 9, whereby the n.sup.+ -type regions 5 and 6 are caused to conduct. When storage data of the memory cell is "0", i.e., when the n.sup.+ -type region 5 stores electrons, the potential of the n.sup.+ -type region 6, having been held at the precharged potential level, is decreased by the conduction of the n.sup.+ -type regions 5 and 6. When, on the other hand, storage data of the memory cell is "1", i.e., the n.sup.+ -type region 5 stores no electron, the potential of the n.sup.+ -type region 6, having been at an intermediate potential level, is increased by the conduction of the n.sup.+ -type regions 5 and 6. Such potential change of the bit line is sensed by the sense amplifier to amplify and extract the same, while the same storage data is refreshed to be rewritten in the memory cell within the same cycle.
With development of a 16k dynamic RAM, remarkably caused are malfunctions (hereinafter referred to as soft errors) in which original storage data are inverted by alpha rays or the like. Such sot errors are caused since electrons within electron-hole pairs generated upon incidence of radioactive rays such as alpha rays are collected in the n.sup.+ -type region 5 serving as a charge storage region and the n.sup.+ -type region 6 serving as a bit line.
In further detail, alpha rays entering the semiconductor chip generate a large number of electron-hole pairs along the range thereof before being stopped by losing energy, and particularly those generated in the depletion layers 13 and 14 are immediately separated by the electric fields in the depletion layers 13 and 14 so that the electrons are collected in the n.sup.+ -type regions 5 and 6 and the holes flow down through the p.sup.- -type substrate 1. The electron-hole pairs generated within the n.sup.+ -type regions 5 and 6 are recombined, and hence the same exert no influence on increase/decrease of the electrons within the n.sup.+ -type ions 5 and 6. Further, within the electron-hole pairs generated in the p.sup.- -type substrate 1, only electrons reaching the depletion layers 13 and 14 by diffusion are collected in the n.sup.+ -type layers 5 and 6 to cause the soft error, while the remaining electrons are recombined in the p.sup.- -type substrate 1.
In the semiconductor memory as shown in FIG. 1, the n.sup.+ -type regions 5 and 6 are enclosed by the p.sup.+ -type region 4 which is higher in impurity concentration than the p.sup.- -type substrate 1, whereby the depletion layers 13 and 14 defined in the interfaces between the n.sup.+ -type regions and 6 and the p.sup.+ -type region 4 are reduced in width and the n.sup.+ -type regions 5 and 6 are increased in capacity. Thus, increased is difference between electron numbers corresponding to "0"and "1"stored in the n.sup.+ -type regions 5 and 6, to provide allowance with respect to the electrons generated by incidence of alpha rays or the like. Further, since the n.sup.+ -type regions 5 and 6 are formed in the p.sup.+ -type region 4, the electrons diffused from the p.sup.- -type substrate 1 are recombined in the p.sup.+ -type region 4 not to reach the n.sup.+ -type regions 5 and 6, while a potential barrier against the electrons is defined in the interface between the p.sup.- -type substrate 1 and the p.sup.+ -type region 4 to prevent passage of low-energy electrons within those diffused from the p.sup.- -type substrate 1. Thus, occurrence of soft errors can be prevented by the structure as shown in FIG. 1.
However, the conventional semiconductor memory of the aforementioned structure requires a considerable time for the process of forming the p.sup.+ -type region 4 which is higher in impurity concentration than the p.sup.- -type substrate 1, while it is difficult to control the impurity concentration and the threshold voltage of the bus transistor and junction pressure resistance are easily changed.